Senior Digital Verification Engineer

Verification

Ref: 1348Monday 6 September 2021

excellent salary and benefits

Enigma People Solutions is recruiting a senior digital verification engineer to join our client’s expanding European Design Centre in Edinburgh, Scotland. Critical to their new product development plans, the Centre designs advanced power control IC's for a broad range of product applications. Our client is recognised world-wide as providing state-of-the-art automotive power integrated circuits.  You will be part of a new verification team which collaborates on the verification of embedded SoCs based on innovative new core architectures.

 

RESPONSIBILITIES

As a senior member of the SoC development team, you will be responsible for developing verification plans based on microarchitecture specifications and using SV/UVM based verification environments to meet the required coverage metrics.

 

Minimum requirements:

  • Knowledge of the embedded SoC design and verification life-cycle with an emphasis on design verification tasks such as: test plan development, test bench creation, test coverage analysis and debug of unexpected design behaviour.
  • Knowledge of CPU, Memory or I/O Subsystem microarchitectures (caches, virtual memory, DMA, memory access optimizations).
  • Experience identifying functional coverage conditions based on microarchitecture specifications
  • Experience of SystemVerilog digital using UVM -SV
  • Expertise building Mixed-Signal testbenches, checkers and tests.
  • Expertise creating and using real-numbered analog behavioral models in SystemVerilog/Verilog-AMS or electrical behavioral models in Verilog-A
  • Experience of script generation for processing results as well as regression control configuration
  • Experience of constrained random verification.
  • Experience of bus-functional model development for verification of custom or industry-standard interfaces.
  • Experience defining team deliverables and tasks, tracking on time execution with a focus on quality.

KEY RELATIONSHIPS

Internal

Liaise with Verification team members.

Liaise with Digital, Analogue, Layout and Systems Group Team members.

External

Liaise with Design Centre’s worldwide.

PERSON SPECIFICATION

Qualifications

Essential

  • The successful candidate will possess at least a Bachelors degree in Electrical and/or Electronic Engineering or equivalent.
  • Languages: System Verilog, Verilog, UVM/OVM, Specman, C/C++, ASM, TCL/TK, Python
  • The successful candidate should have excellent communication skills
  • The successful candidate should be able to demonstrate excellent documentation skills

Desirable

Preference will be given to candidates who also possess the following:

  • Tools: Unix, Cadence Incisive, Cadence vManager
  • Digital mixed signal Testbench building expertise
  • Microprocessors: ARM Cortex-M.
  • Digital design experience with RTL coding and SCAN methodologies.

Skills, Knowledge and Aptitudes

Candidates should also be able to demonstrate:

  • Good presentation skills in English and the ability to present technical information in a clear and concise manner.
  • A high level of commitment and self-motivation
  • The ability to work as part of a world-wide development team with diverse engineering disciplines.
  • Experience of problem-solving and analytical skills.

 

TRAVEL REQUIREMENTS

National Travel: 5-10%

International Travel: 5-10%

 

Travel Locations

Dependent on work that may arise, most likely travel will be within Europe, the Americas and Asia.