Digital Verification Engineer


Ref: 1300Sunday 9 May 2021

£35,000 to £45,000 plus benefits

Enigma People Solutions is recruiting a Digital Verification Engineer to work on state-of-the-art automotive power IC’s. You will be joining an expanding team that is recognised world-wide as providing market leading advanced power control IC’s for a broad range of product applications. Working from our client’s European Design Centre in Edinburgh your work will be critical to new product development plans. You will be part of a new verification team which collaborates on the verification of gate-driver ICs and embedded SoCs based on innovative new core architectures.


  • Review and analysis of IP and system-level design specifications to drive identification of functional coverage conditions.
  • Propose and implement appropriate verification solutions to meet functional coverage requirements.
  • Verilog/SystemVerilog/UVM testbench development.
  • Code and functional coverage analysis and debug of RTL and gate-level simulations.
  • Maintenance and continuous improvement of verification methodology, automation and regression control.



  • Collaborate with digital design and verification engineers.
  • Collaborate with analog design engineers on mixed signal simulation debug.
  • Review of requirements with system engineers.


  • Liaise with off-site design teams as required.
  • Communicate with EDA and tool vendors.





  • The successful candidate will possess at least a Bachelors degree in Electrical and/or Electronic Engineering or equivalent.
  • Languages: System Verilog, Verilog, UVM/OVM, Specman, C/C++, ASM, TCL/TK, Python
  • The successful candidate should have excellent communication skills
  • The successful candidate should be able to demonstrate excellent documentation skills


  • Knowledge of the embedded SoC design and verification life-cycle with an emphasis on design verification tasks such as: test plan development, test bench creation, test coverage analysis and debug of unexpected design behavior.
  • Knowledge of CPU, Memory or I/O Subsystem microarchitectures (caches, virtual memory, DMA, memory access optimizations).
  • Experience identifying functional coverage conditions based on microarchitecture specifications
  • Experience of SystemVerilog digital & mixed-signal verification.
  • Experience of script generation for processing results as well as regression control configuration
  • Experience of constrained random verification.
  • Experience of bus-functional model development for verification of custom or industry-standard interfaces.

Skills, Knowledge and Aptitudes


  • Strong skills in UVM testbench development.
  • Languages: SystemVerilog, Verilog, C, ASM
  • Scripting: Python, Perl
  • Knowledge of digital design techniques
  • Knowledge of the overall front-to-back digital design flow.
  • Good verbal and written communication skills
  • Ability to work in a multi-cultural team environment
  • Candidates should also be able to demonstrate:
    • Good presentation skills in English and the ability to present information in a clear and concise manner
    • A high level of commitment and self-motivation
    • The ability to work as part of a world-wide development team with diverse engineering disciplines