Digital UVM Verification Engineer


Ref: 1230Tuesday 28 January 2020

£35,000 - £42,000 + benefits

Enigma People Solutions is looking for a Digital UVM Verification Engineer to join our multinational electronics client’s Imaging Division based in Edinburgh. The position of Digital UVM Verification Engineer requires a motivated individual with strong communication and team-working skills. You will be passionate about verification, with a good knowledge of UVM and enjoy understanding the full system-level view of a product.


Throughout our decade long relationship with this client, we have placed numerous candidates; many of whom are still happily there, working on cutting edge technologies for one of Europe’s most innovative tech giants. By joining the team in Edinburgh, you’ll become part of a R&D team that is at the forefront of this company’s technological advance. You’ll be working in great environment (newly refurbished office completed in summer of 2017), with on site test labs and within walking distance to Edinburgh city centre. Great benefits and competitive salary is on offer, as well as clear career progression.


You will play an important role in the development of new products. This will involve a broad range of verification tasks covering, spec analysis, test plan development, system understanding through technical document review and interaction with other teams (Digital design, Analogue design, Embedded Firmware design, System Architecture and Applications) and implementation of the required verification tests.



You will be responsible for the design and implementation of the project’s UVM environment including:

  • SystemVerilog test benches
  • Design and implementation of the required tests for a specific product
  • Script development for automation of non-regression testing
  • Analysis of test results and presentation for review in a test report
  • Contributing to quality reviews with the technical manager.


Key skills & experience

  • Relevant degree level qualification
  • Solid understanding of digital theory, including static timing analysis (STA) and high-speed/low-power design techniques.
  • Proficiency in Verilog HDL/System Verilog, and the C programming language
  • Proficiency in SystemVerilog and Universal Verification Methodology (UVM)
  • Practical experience in using and creating SystemVerilog test benches
  • Good knowledge of scripting languages (PERL, Python…)
  • Good knowledge of version control management (SVN, Git…)



  • Income Protection - 2/3rds base salary if permanently unable to work
  • Life Assurance - 4x annual salary
  • Private Medical Insurance - fully expensed for family (pay only the taxable benefit)
  • Free Health Check-ups - every two years
  • Stakeholder Pension - up to 7.5% from the company
  • Pension Salary Sacrifice - we give 100% of NI saving (12.8%)
  • Flexible Holiday - buy or sell up to 5 days
  • Cycle Scheme - save ~50% on a bike
  • Child Care Vouchers - tax efficient child care
  • Accident Insurance - up to 5x salary
  • Social Club - subsidised membership to Escapees


For more information, submit your CV or get in touch with Dan on 0131 510 8150 or