Digital IC Design Principal Engineer, Dresden, Germany


Ref: 1315Friday 9 April 2021

£55,000 - £85,000 DOE plus benefits including: 35 days holiday, Vitality Health care and flexible working

Enigma People Solutions is recruiting a Digital IC Design Verification Engineer to work on state-of-the-art automotive power IC’s. You will be joining an expanding team that is recognised world-wide as providing market leading advanced power control IC’s for a broad range of product applications. Working from our client’s European Design Centre in Dresden, Germany. your work will be critical to new product development plans. You will be part of a new verification team which collaborates on the verification of gate-driver ICs and embedded SoCs based on innovative new core architectures.

Our client's design team develops custom automotive centric ICs using ARM Cortex-M based micro-controllers and integrate Analog and mixed signal, RF and Power Management IPs bringing a complete solution to our international customer base.

In this position, the IC Engineer is responsible for managing and executing all activities associated with design, integration, verification and maintenance of digital IPs integrated in IC used in the area of embedded micro controller-based system solutions. The IC design responsibilities will include building digital components based on customer application specific requirements or IP standards and support the team to complete the design including top level integration, physical design support (constraints and gate level verification).

Job Responsibilities:

  • Work with System team to define IP specification.
  • Write RTL to implement digital IP based on a design specification.
  • Write implementation document of the digital IP.
  • Develop block level test bench, test cases to check basic functionality of the design.
  • Work in integration of digital IP at the chip level.
  • Run RTL and gate level functional verification, debug failures, manage bug tracking, and analyze and close coverage.
  • Work with FW engineer for the integration of the digital IP functionality at the system level in the application.
  • Support application engineer in the debug of the digital IP on the silicon.

Main Requirements:

  • Master’s degree in electrical engineering
  • 10 Years of relevant experience
  • Develop RTL (Verilog) and detailed documentation.
  • Support synthesis, STA, and logic equivalency checks.
  • RTL & gate level simulations.
  • Demonstrate knowledge of designing digital blocks using Verilog code.
  • Demonstrated knowledge of digital circuit simulation tools and front-end environments, particularly Cadence based.
  • Demonstrated knowledge of lab equipment tools such a logic analyzer
  • Demonstrated knowledge of revision control systems
  • Programming in ruby, python, perl languages
  • Excellent communication skills
  • Report progress to the team leader on a regular basis.