Posted August 02, 2017 | Electronics | No Comments »

[Guest Blog] Key Considerations for Your Hardware Prototyping

One of the most exciting stages of an engineering project is when the hardware arrives in the lab for the first-time ready for commissioning before integration testing. You will have been planning for this day for a long time (hopefully) as the cost of identifying and correcting errors later on in the production run only increases. This typically can mean long hours for all the engineers on the project so, how can we try and reduce this time and minimise the issues which may arise?

3 Key Considerations:

1. Think what you will test from day one

The aim of the testing is to ensure you are delivering a safe system which meets the user’s specified requirements. Before we can focus on the higher level functional requirements, we need to ensure the underlaying hardware is correct. To correctly perform this testing, we will need to generate several test plans (functional, hardware etc) which address what is to be tested and how.

This test plan will detail the requirements and how we intend to verify them. It will also define the expected results (do not forget tolerances) otherwise, how else can you be expected to know if it performs as required or not?

[Guest Blog] Key Considerations for Your Hardware Prototyping

Generating these test plans early will ensuring we have provided sufficient test points in the design required to perform the testing.

2. Think about what to include in the design

[Guest Blog] Key Considerations for Your Hardware Prototyping 1

During the design of the hardware, several design features and functions may need to be included to allow testing of the board with greater ease. The most simple and often implemented test provision is placing test points on all voltage rails. Being able to monitor the outputs of clocks and resets is also important, for this reason, it is good practice to place test points on the reset line and correctly terminate an unused clock buffer and add test points allowing the clock to be probed with ease. Many modern high-performance devices also have on die temperature diodes which can be used during your testing to determine the junction temperature of the die is acceptable, provided you can access these points.

3. Simple RTL

[Guest Blog] Key Considerations for Your Hardware Prototyping - Simple RTL

If you have a complicated design at both the hardware and FPGA level it can be best to develop a more simplified cut-down version of the RTL to aid in the testing of the board and the interface between the FPGA and the peripheral. This is especially the case if you are designing high-speed interfaces. This cut down RTL could be used in conjunction with chip scope to capture data and block rams which have been pre loaded with data patterns to act as stimulus. This can especially be the case when using ADCs and DACs connected to an FPGA the reprogrammable nature of the FPGA should be utilized to the maximum to develop designs which will allow parametric testing of the ADC and DAC, for instance, Noise Power Ratio, Spurious Free Dynamic Range and effective number of bit calculations. You should also aim to capitalize on the resources provided by the FPGA especially system monitor and XADC which can be very useful for monitoring the voltage rails on die and hence helping verify the power integrity analysis

Here are a few extra considerations you might want to make to ensure things run as smooth as possible:

  • Accessibility of test points and debug headers to ensure you can actually access them. If they are on power lines, ensure they are protected in case of shorts.
  • How you can test the board on its own.  Will you need any special type test equipment to enable you to test it? When will it be available?
  • JTAG and boundary scan technology should also be considered to provide a virtual bed of nails to test the interconnects between devices on the board.

Once you get the hardware in the lab,the testing is generally split into two sections the first section is checking the hardware integrity i.e. can it be powered on safely and is it suitable for further testing? During this stage, you will check the board has been manufactured and populated correctly, that the voltage rails are safe to turn on and then will come the moment of truth when you have to apply power to the board for the first time. This is always a nerve wracking moment…

Once you have applied power you will be looking at the current drawn against your projections, are the clocks at the correct frequency, is the jitter acceptable? does the protection circuitry (over voltage / under voltage), resets and sequencing function as desired. This is the basic engineering tests that will be your first priority, however; you will soon progress to wanting to test the more complex interfaces and then the performance.

Some of these may be able to be tested via JTAG / Boundary scan however it is only really testing at speed that you can relax a little (you can never truly relax even after all the qualification testing). It is, therefore, a great idea to have developed some simple test code for your FPGA or microprocessor to prevent you having to debug both the FPGA/Microprocessor design and the board design. I am sure we have all spent many hours looking into is the issue with the board, FPGA, processor or even worse the ASIC.

Once you have completed the integrity checks you can then proceed to test the functionality and working out what changes you need to make to the next iteration if any.

What if it does not go to plan? The first thing to do is not panic, for many issues, you will probably not be the first person to face this issue(s) though it may feel like it. Revisit the design schematics, layout and read the data sheets and any errata’s again or give me a call.


This blog was originally written by Adam Taylor, engineering leader and world recognised expert in FPGA / System on Chip and Electronic Design. You can find this and loads more at

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